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93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.8 Write
The WRITE instruction is followed by 8 bits (if ORG is
low or A-version devices) or 16 bits (if ORG pin is high
or B-version devices) of data, which are written into the
specified address. For 93AA46A/B/C and 93LC46A/B/C
devices, after the last data bit is clocked into DI, the
falling edge of CS initiates the self-timed auto-erase and
programming cycle. For 93C46A/B/C devices, the self-
timed auto-erase and programming cycle is initiated by
the rising edge of CLK on the last data bit.
The DO pin indicates the Ready/ Busy status of the
device if CS is brought high after a minimum of 250 ns
low (T CSL ). DO at logical ‘ 0 ’ indicates that programming
is still in progress. DO at logical ‘ 1 ’ indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
Note: After the Write cycle is complete, issuing a
Start bit and then taking CS low will clear
the Ready/ Busy status from DO.
FIGURE 2-8:
WRITE TIMING FOR 93AA AND 93LC DEVICES
T CSL
CS
CLK
DI
1
0
1
A N
???
A0
Dx
???
D0
T SV
T CZ
DO
High-Z
Busy
Ready
High-Z
T WC
FIGURE 2-9:
WRITE TIMING FOR 93C DEVICES
T CSL
CS
CLK
DI
1
0
1
A N
???
A0
Dx
???
D0
T SV
T CZ
DO
High-Z
Busy
Ready
High-Z
T WC
DS21749J-page 10
? 2002-2011 Microchip Technology Inc.
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